FIG. 4 is a block diagram showing a system including a BUCK regulator 20, an LDO regulator 25, and a field programmable gate array (FPGA) 30 in a conventional arrangement. A raw voltage source (e.g., a battery) provides a relatively high, unregulated voltage VRAW that is supplied to BUCK regulator 20. BUCK regulator 20 supplies a relatively high regulated voltage VI/O (e.g., 3.3V) to the input/output (I/O) circuitry of FPGA 30 and to LDO regulator 25, and LDO regulator 25 provides a relatively low regulated voltage VCORE (e.g., 2.5V) to the core logic circuitry of FPGA 30.
FIG. 5 is a timing diagram illustrating the various voltages generated in the system of FIG. 4 during startup. First, unregulated voltage VRAW ramps up, and then after a brief delay BUCK regulator 20 begins generating relatively high regulated voltage VI/O. Finally, after a time delay TDELAY needed to allow regulated voltage VI/O to reach a high enough voltage level to allow regulation, LDO regulator 25 begins to generate relatively low regulated voltage VCORE.
The conventional arrangement described with reference to FIGS. 4 and 5 is highly efficient in that it minimizes the consumption of energy and the generation of heat. In particular, switching regulators, such as BUCK regulator 20, are able to regulate the higher I/O bus using the raw unregulated voltage VRAW in more efficient manner than linear regulators, such as LDO regulator 25. In contrast, linear regulators have an advantage over switching regulators in that they produce a relatively “quiet” (i.e., noise-free) regulated output voltage, but are not as efficient, particularly when the raw unregulated voltage VRAW is significantly higher than the desired regulated output voltage VCORE. Therefore, to maximize efficiency, BUCK regulator 20 and LDO regulator 25 are connected in the series arrangement shown in FIG. 4 such that LDO regulator 25 is driven by regulated output voltage VI/O, which is closer to the desired regulated output voltage VCORE than raw unregulated voltage VRAW.
A problem arises when complex electronic systems, such as the system shown in FIG. 4, that incorporate electronic devices such as microprocessors, FPGAs, and digital application specific integrated circuits (ASICs), require sequencing of their power supplies in a manner that is inconsistent with the timing diagram shown in FIG. 5. In particular, it is often necessary for the core logic circuitry of FPGA 30 to receive power before the I/O circuitry so that peripheral devices remain under control during power up and power down sequences. Unfortunately, as indicated in FIG. 5, the power efficient conventional arrangement causes the relatively low regulated core voltage VCORE to necessarily lag the relatively high regulated I/O voltage VI/O, which is contrary to the desired startup supply voltage sequence.
One current approach to addressing the sequencing problem described above is to use discrete diodes and multiple regulators to provide the necessary sequence. However, this approach is inconvenient and expensive.
What is needed is a LDO regulator that addresses the sequencing problem described above without requiring multiple discrete components.